1. Field of the Invention
The present invention is directed in general to the field of semiconductor chip packages. In one aspect, the present invention relates to a lead frame design and packaging scheme for producing lead frame packages.
2. Description of the Related Art
Quad Flat No-Lead (QFN) and Power Quad Flat No-leads (PQFN) packages are used to encapsulate one or more integrated circuit die while retaining exposed pads which physically and electrically connect integrated circuit die to printed circuit boards (PCB). These QFN and PQFN packages are surface-mount technologies that connect integrated circuit dies to the surfaces of PCBs without through-holes using perimeter lead pads on the bottom of the package to provide electrical contact to the PCB. Conventional QFN/PQFN packaging approaches have performed injection molding after mounting the integrated circuit die on the lead frame having selectively recessed leads and before singulating individual QFN/PQFN packages. With these approaches, mold compound material is formed in the recesses, thereby impairing visibility of the solder fillets and reducing the available solderable area which decreases the overall solder joint strength and reliability between the QFN/PQFN package and PCB/motherboard.
Accordingly, a need exists for an improved integrated circuit chip package and manufacture method that addresses various problems in the art that have been discovered by the above-named inventors where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.